The First International Workshop on
Challenges on Massively Parallel Processors
(CMPP 2011)

CMPP11_logo.pngto be held in conjunction with ICNC'11
Osaka, Japan, November 30-December 2, 2011

Call for paper in
PDF ----> fileCMPP11_CFP.pdf
TXT ----> fileCMPP2011_CFP.txt
Please link to

Workshop summary

Implemented multiple processor cores on an integrated silicon die, a new Moore’s law has been developed and has become popular in the industrial market, called massively parallel environment. It is generally referred as manycore/multicore processors such as the efforts to Multicore CPUs from Intel and AMD, GPUs from NVIDIA and ATI and CELL from IBM, for instance. This workshop, CMPP will focus on dissemination opportunities for researchers from over the world to present advanced technologies and research results. Moreover, the eager discussion will be expected in the congress to exchange the opinions to promote the future technologies for massively parallel processors.


Authors are invited to submit manuscripts that present original unpublished research, including the development of experimental or commercial systems. Work focusing on emerging technologies is especially welcome. Topics of interest include, but are not limited to:

  • Challenges for GPU Computing
    • Performance analysis and algorithm for applications from various areas
    • Supercomputing on GPU clusters
    • Novel techniques on performance acceleration for GPU computing
    • Compiler techniques and instruction scheduling for performance improvement
  • Challenges for architectures of massively parallel systems
    • Future system design
    • Massively parallel system on FPGA / LSI
  • Challenges for novel models and algorithms targeted to manycore/multicore systems
    • Modeling and algorithms from various areas on massively parallel environment
    • Stream computing
    • Performance acceleration models for future performance demands
    • Load balancing and task scheduling on massively parallel environment
  • Challenges for applications
    • Algorithms and practical performance analysis for industrial/numerical/scientific applications

Submission Instruction

Prospective authors are encouraged to submit an electronic version of an original, unpublished manuscript in PDF using EasyChair by July 18, 2011. If you do not have an EasyChair account, you must create it first. Submissions should include abstract, keywords, the e-mail address of the corresponding author, and must be from 5 to 7 pages using IEEE Manuscript Templates for Conference Proceedings. Submissions imply the willingness of at least one author to register, attend the workshop, and present the paper. Accepted and presented papers will be published by Conference Publishing Service and archived to IEEE Xplore and CSDL digital libraries. Also they are arranged for indexing through INSPEC, EI (Compendex), Thomson ISI, and other indexing services.

Important Dates

  • Submission: Extended to August 3, 2011
  • Notification of paper acceptance: August 20, 2011
  • Submission of camera-ready papers: September 9, 2011

Special Issue on Journal

The selections of the accepted papers on the workshop will be invited for publication at a special issue on International Journal of Networking and Computing (

Special Tutorial Session

We will organize a special tutorial session as a part of ICNC. Preliminary titles are listed below;

"TSUBAME2.0: A Petascale GPU-accelerated Supercomputer" by Prof. Toshio Endo (Tokyo Institute of Technology, Japan)

Abstract: General-purpose graphics processing unit (GPGPU) computing technology is becoming attractive and popular because of its superior power-performance ratio. By using this technology, Tokyo Institute of Technology has installed a new petascale supercomputer, called TSUBAME2.0 in November 2010. This system includes 4,224 NVIDIA Tesla M2050 GPUs distributed over 1,408 computing nodes, and enjoys peak performance of 2.4 Petaflops, which became No.4 supercomputer in the world as of 2010. While users can utilize this system as a large Linux cluster by running CPU parallel programs, they can largely accelerate the performance with GPGPU technology. The area of accelerated applications on TSUBAME2.0 includes weather simulation, earthquake simulation, molecular dynamics application and DNA analysis, etc. TSUBAME2.0 also adopts other technologies to achieve “green” petascale supercomputer that accommodates real large scale applications, including 7PB shared storage, solid state drives (SSD) as local storage, and modular cooling system racks.

"All about RICC: RIKEN Integrated Cluster of Clusters", Dr. Maho Nakata (RIKEN, Japan)

Abstract: This is an introduction to RIKEN's supercomputer RICC (RIKEN Integrated Cluster of Clusters) that has been in operation since August 2009. Its total performance is 93.3TFlops, which was ranked 40th in the top 500 supercomputers, and was the fastest PC cluster system in August 2009. One of the motivations for RICC was to create an environment for programmers to develop software for the next generation's supercomputer systems that may be massively parallelized using GPUs. RICC can run computational jobs on 8192 cores. This number can be increased with GPU accelerators. This super parallel PC clusters consists of 1024 nodes where each node contains 8 cores, 12G bytes memory, and 500G bytes of storage. These cores are interconnected via Infiniband.

"Invitation to OpenCL" by Mr. Pablo Lamilla Alvarez (Kochi University of Technology, Japan)

Abstract: The recent advancement in GPU technology has attracted researchers who need intensive computing to the GPU-based computing (GPGPU) field because of its high and inexpensive performance. However, GPGPU programming platforms are traditionally vendor- or hardware-specific, which complicate the access to the computer power of heterogeneous processors from a single host. The recently released OpenCL is expected to become a standard for massively parallel heterogeneous processors. This tutorial introduces the OpenCL, explaining the characteristics of the environment and describing in detail the basic structure of OpenCL program. The tutorial also presents and evaluates various techniques to improve the performance of OpenCL applications.


Workshop co-chairs

  • Shinichi Yamagiwa (Kochi University of Technology / JST PRESTO, Japan)
  • Koji Nakano (Hiroshima University, Japan)

Program Committees

  • Micheal Stiber (University of Washington Bothell, USA)
  • Munehiro Fukuda (University of Washington Bothell, USA)
  • Koichi Wada (University of Tsukuba, Japan)
  • Oliver Sinnen (University of Auckland , New Zealand)
  • Seiji Yunoki (RIKEN ASI/AICS / JST CREST, Japan)
  • Kiminori Matsuzaki (Kochi University of Technology, Japan)
  • Leonel Sousa (TU Lisbon / IST / INESC-ID, Portugal)
  • Maho Nakata (RIKEN, Japan)
  • Masahiko Okumura (Japan Atomic Energy Agency, Japan)
  • Akihiro Kishimoto (Tokyo Institute of Technology / JST PRESTO, Japan)
  • Toshio Endo (Tokyo Institute of Technology, Japan)
  • Vitor Silva (IT/University of Coimbra, Portugal)
  • Gabriel Falcao (IT/University of Coimbra, Portugal)

Steering committees

  • Shinichi Yamagiwa (Kochi University of Technology / JST PRESTO, Japan)
  • Naka Gotoda (Kochi University of Technology / JSPS, Japan)

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